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WL-CSP Assembly and Testing Service

Service

Offer the downsizing and lightening package “WL-CSP”

The wafer level chip size package (WL-CSP) is the most suitable for downsizing and lightening for mobile system ,and contribute to High-performance and multi-function by Cu RDL technology and Plating technology (Cu,Ni,Au,SnAg). Also we will provide any foundry model for customer request.

  • We can deal with Cu RDL process,singulation process,Final Test,tape & reel packing consistently.
  • Also we will deal with custom process and partial process. Please contact us.
  • Solutions
  • Structure and Feature
  • Technology roadmap
  • New technology

WL-CSP

Small and Thin Package for Smart Phone and Wearable devices

  • Many experience and know-how since 1999
  • High reliability and many automobile experience in Mold type CSP
  • Very thin and narrow pitch terminals in Mold-less type CSP
  • Flexible production scheme by co-operating OSATs
  • WL-CSP lineup : click here
 

Thick Cu RDL (Re-Distribution Layer)

Improving Performance/Miniaturization/Multifunction for Power devices

  • On resistance decrease by thick Cu RDL
  • Pad layout free and I/O Pad size reduction
  • Thick insulator film enables High voltage operation
 

Application Technology

Next Generation Package by LAPIS Semiconductor novel technologies

  • Realizing Multi chip PKG, Module and Fan Out PKG by merging RDL/Cu pillar technologies and Packaging technologies
 

WL-CSP major lineups

LAPIS Semiconductor will propose best solution
to satisfy customer's requests

  • High reliability (Automobile, Industrial, Medical) : Mold Type package
  • Very thin (Board built-in parts) : 0.2mm
  • Narrow pitch : 0.15mm
  • Very narrow pitch (Cu Pillar) : 0.10mm
  • High density : Multi-level RDL, MC-WLP
  • Others : Backside treatment,Low temperature insulator,Terminal formation (Sn-Ag/Au/Ni plating) including customization

 

Mold Type

Mold-less Type

Structure

 
 
 
 
 

Features

Chip surface protection property/Low stress at mounting to board

Fine pitch terminal / Very thin type CSP

Process step elimination by Cu+ / Ni continuous plating

Terminal treatment for board built-in parts

Ultra fine pitch terminal / Very thin type CSP

Production
start

1999

2010

2013

2014

2017

Package

thickness

≥0.3mm

≥0.2mm

≥0.3mm

≥0.2mm

≥0.2mm

Terminal
pitch

≥0.3mm
(Printing)
≥0.4mm
(Ball)

≥0.15mm
(Printing)

≥0.4mm
(Ball)

≥0.35mm
(Plating)

0.1 to 0.13mm

Light
shielding
roperty

Yes

No

No

No

No

Device
protection
property

Excellent

Good

Good

Good

Good

Stress
at
mounting
to
board

Low

Normal

Normal

Normal

Low

Application
results

Automobile (Transmission)

Smart Phone (PMIC)

Mobile Game

(DCDC)

Smart Phone

(RF IC)

Smart Phone

(DCDC)

Industrial

(Sensor IC)

Consumer

(PMIC)

Smart Phone

(RF IC)

Wearable

(DCDC)

Smart Phone

(DCDC)

What's WL-CSP

Wafer Level - Chip Size Package (WL-CSP) is The latest model package. WL-CSP has the structure of making Cu RDL,Molding ng at wafer l,terminal formievel without using lead frame, gold wire. And it has the basic characteristics and reliability of WL-CSP is equal to conventional package, and realize downsizing and lightening. *µLAPIS™series

 

The advantage of WL-CSP

The advantage of WL-CSP

  • smallest, thinnest and lightest
  • Low cost
  • Saving resources (Ecology)
  • Reduction of material dead stock
  • Shortening TAT( turn around time)
  • It is possible to wire optionally
 

WL-CSP Process

We can deal with insulation layer,Cu RDL process,Si Grind,
Final Test,Dicing, tape&reel packing consistently.
reducing cost for customers.

 

Technology roadmap

 

Cu RDL for High current application

Thick Cu RDL technology and
Surface treatment technology

Features
  • Aluminum Pad layout free and I/O Pad size reduction
  • On resistance decrease by very thick(13 to 20µm)Cu RDL
  • Surface treatment optimization for connecting wire material
Applications
  • Motor driver / LED / Coil / Operational amplifier
Thick Cu specification(Normal)
  • Cu/Ni/Au Thickness : 13µm/3µm/0.5µm
  • L/S : 30µm/30µm
 
 

Cu RDL technology for Multifunction and High voltage operation

Cu RDL and Terminal treatment technology
(Au/Ni/Sn-Ag plating)

    Features
  • Multi-level Cu RDL technology for Multifunction and Improving performance
  • On resistance decrease by Cu RDL
  • Thick insulator increase operation voltage (actual result up to 600V)
  • Plating surface improvement by plating technology such as filling plating for Wire bond, Flip chip bonding
  • Applications
  • Power device / Sensor and control device / Millimeter wave etc.
  •  
 

Next Generation Package : Multi chip WLP

Next Generation Package by Lapis novel technologies

Realizing Multi chip PKG, Module and Fan Out PKG by merging RDL/Cu pillar technologies and Packaging technologies.


    Features
  • Small package by High Cu Post and Chip on Wafer technology
  • Decrease resistance by eliminating connecting wire and substrate conductive lines
  • High Reliability performance
  •